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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-09 20:10:29 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-25 12:51:29 +0000 |
| commit | 47fd797f1ecd303da3263b180904a7a0b0e18581 (patch) | |
| tree | c1bdd2b5184ea89bb373922edbeb8e51602c4df0 /src/arch/arm/isa.cc | |
| parent | b045de7e6969d5a40d4a3f9b178844cc911ac4c2 (diff) | |
| download | gem5-47fd797f1ecd303da3263b180904a7a0b0e18581.tar.xz | |
arch-arm: Inital vector rename mode depending on A32/A64
Change-Id: I6b99833641b0ab6534471d5ff3ca5d3791285481
Reviewed-on: https://gem5-review.googlesource.com/c/15599
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 6cbf8db90..97de97e6e 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -62,7 +62,7 @@ ISA::ISA(Params *p) : SimObject(p), system(NULL), _decoderFlavour(p->decoderFlavour), - _vecRegRenameMode(p->vecRegRenameMode), + _vecRegRenameMode(Enums::Full), pmu(p->pmu), impdefAsNop(p->impdef_nop) { @@ -103,6 +103,10 @@ ISA::ISA(Params *p) haveGICv3CPUInterface = true; } + // Initial rename mode depends on highestEL + const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) = + highestELIs64 ? Enums::Full : Enums::Elem; + initializeMiscRegMetadata(); preUnflattenMiscReg(); |