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| author | Jordi Vaquero <jordi.vaquero@metempsy.com> | 2019-08-06 15:49:14 +0200 |
|---|---|---|
| committer | Jordi Vaquero <jordi.vaquero@metempsy.com> | 2019-08-07 14:30:51 +0000 |
| commit | 92abad849186256f4a4b309ed867d375d07c5c63 (patch) | |
| tree | 757b4fb7225fe35d8739ad2950aaa51042a362f2 /src/arch/arm/isa.cc | |
| parent | 676d5fe4e882c9d073964a72c619024306fd279a (diff) | |
| download | gem5-92abad849186256f4a4b309ed867d375d07c5c63.tar.xz | |
arch-arm: adding register control flags enabling LSE implementation
Added changes on arch-arm architecture to accept Atomic instructions
following ARM v8.1 documentation. That includes enabling atomic bit
in ID registers and add have_lse variable into arm system.
Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19809
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 23738c6ae..299698d3d 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -93,6 +93,7 @@ ISA::ISA(Params *p) haveSVE = system->haveSVE(); havePAN = system->havePAN(); sveVL = system->sveVL(); + haveLSE = system->haveLSE(); } else { highestELIs64 = true; // ArmSystem::highestELIs64 does the same haveSecurity = haveLPAE = haveVirtualization = false; @@ -102,6 +103,7 @@ ISA::ISA(Params *p) haveSVE = true; havePAN = false; sveVL = p->sve_vl_se; + haveLSE = true; } // Initial rename mode depends on highestEL @@ -393,6 +395,10 @@ ISA::initID64(const ArmISAParams *p) miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4, haveCrypto ? 0x1112 : 0x0); + // LSE + miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( + miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20, + haveLSE ? 0x2 : 0x0); // PAN miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits( miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20, |