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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-04-10 15:45:30 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-04-25 12:48:59 +0000 |
| commit | e8d0b755eadffb0203b966479f55a75281522b18 (patch) | |
| tree | 1ec6d8dccfc1f01e2db7f35894a7bd51d84cf323 /src/arch/arm/isa.cc | |
| parent | 670d080aa1669a67b30da5fad995a4377d23d77d (diff) | |
| download | gem5-e8d0b755eadffb0203b966479f55a75281522b18.tar.xz | |
arch-arm: Remove un-needed hyp flag in TLBI operations
The hyp flag was probably a legacy pre-v8 flag distinguishing
invalidation targeting PL2 translation regime (hyp mode).
Since the introduction of target_el parameter, hyp boolean is not needed
anymore. The patch works by setting the hyp flag in the flush* methods
in the TLB automatically by checking if target_el == EL2.
Change-Id: I798009e09ff24a383dea871e348188bae2685e8e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18389
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index d5d88e628..654608a08 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1191,7 +1191,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) scr = readMiscReg(MISCREG_SCR, tc); TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, - mbits(newVal, 31,12), false); + mbits(newVal, 31,12)); tlbiOp(tc); return; @@ -1204,7 +1204,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) scr = readMiscReg(MISCREG_SCR, tc); TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, - mbits(newVal, 31,12), false); + mbits(newVal, 31,12)); tlbiOp.broadcast(tc); return; @@ -1220,7 +1220,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) scr = readMiscReg(MISCREG_SCR, tc); TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns, - mbits(newVal, 31,12), true); + mbits(newVal, 31,12)); tlbiOp(tc); return; @@ -1233,7 +1233,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) scr = readMiscReg(MISCREG_SCR, tc); TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns, - mbits(newVal, 31,12), true); + mbits(newVal, 31,12)); tlbiOp.broadcast(tc); return; @@ -1329,7 +1329,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) { assert32(tc); - TLBIALLN tlbiOp(EL1, false); + TLBIALLN tlbiOp(EL1); tlbiOp(tc); return; } @@ -1338,7 +1338,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) { assert32(tc); - TLBIALLN tlbiOp(EL1, false); + TLBIALLN tlbiOp(EL1); tlbiOp.broadcast(tc); return; } @@ -1347,7 +1347,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) { assert32(tc); - TLBIALLN tlbiOp(EL2, true); + TLBIALLN tlbiOp(EL2); tlbiOp(tc); return; } @@ -1356,7 +1356,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) { assert32(tc); - TLBIALLN tlbiOp(EL2, true); + TLBIALLN tlbiOp(EL2); tlbiOp.broadcast(tc); return; } @@ -1538,7 +1538,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) scr = readMiscReg(MISCREG_SCR, tc); TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, - static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); + static_cast<Addr>(bits(newVal, 43, 0)) << 12); tlbiOp(tc); return; @@ -1551,7 +1551,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) scr = readMiscReg(MISCREG_SCR, tc); TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, - static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); + static_cast<Addr>(bits(newVal, 43, 0)) << 12); tlbiOp.broadcast(tc); return; |