diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:08 -0500 |
---|---|---|
committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:08 -0500 |
commit | 6aa229386dcd8b6d15529a0acdf8e3040dfeb337 (patch) | |
tree | a8ec8aa6fc3aae1f9fdb9a0aecae6d6b53569eed /src/arch/arm/isa.hh | |
parent | 7ff24c877750a24507afb87eebe14cd1df40a5fa (diff) | |
download | gem5-6aa229386dcd8b6d15529a0acdf8e3040dfeb337.tar.xz |
ARM: Implement a function to decode CP15 registers to MiscReg indices.
Diffstat (limited to 'src/arch/arm/isa.hh')
-rw-r--r-- | src/arch/arm/isa.hh | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index c64f7bef9..080298158 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -152,6 +152,11 @@ namespace ArmISA cpsr.t = 0; return cpsr; } + if (misc_reg >= MISCREG_CP15_UNIMP_START && + misc_reg < MISCREG_CP15_END) { + panic("Unimplemented CP15 register %s read.\n", + miscRegName[misc_reg]); + } return readMiscRegNoEffect(misc_reg); } @@ -205,6 +210,11 @@ namespace ArmISA tc->setNextPC(npc); } + if (misc_reg >= MISCREG_CP15_UNIMP_START && + misc_reg < MISCREG_CP15_END) { + panic("Unimplemented CP15 register %s wrote with %#x.\n", + miscRegName[misc_reg], val); + } return setMiscRegNoEffect(misc_reg, val); } |