ARM: Implement a function to decode CP15 registers to MiscReg indices.

1 files changed, 10 insertions, 0 deletions

diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index c64f7bef9..080298158 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -152,6 +152,11 @@ namespace ArmISA
                     cpsr.t = 0;
                 return cpsr;
             }
+            if (misc_reg >= MISCREG_CP15_UNIMP_START &&
+                misc_reg < MISCREG_CP15_END) {
+                panic("Unimplemented CP15 register %s read.\n",
+                      miscRegName[misc_reg]);
+            }
             return readMiscRegNoEffect(misc_reg);
         }
 
@@ -205,6 +210,11 @@ namespace ArmISA
 
                 tc->setNextPC(npc);
             }
+            if (misc_reg >= MISCREG_CP15_UNIMP_START &&
+                misc_reg < MISCREG_CP15_END) {
+                panic("Unimplemented CP15 register %s wrote with %#x.\n",
+                      miscRegName[misc_reg], val);
+            }
             return setMiscRegNoEffect(misc_reg, val);
         }