ARM: Add support for the clidr register.

This register will always report 0 caches as implemented. It's not clear how
to find out how many there really are when dealing with an arbitrary
hierarchy.

1 files changed, 5 insertions, 0 deletions

diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index dd80976bb..1d8f14cab 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -164,6 +164,11 @@ namespace ArmISA
                 panic("Unimplemented CP15 register %s read.\n",
                       miscRegName[misc_reg]);
             }
+            switch (misc_reg) {
+              case MISCREG_CLIDR:
+                warn("The clidr register always reports 0 caches.\n");
+                break;
+            }
             return readMiscRegNoEffect(misc_reg);
         }