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author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:09 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:09 -0500 |
commit | e658b6fed46afb0b587dba037bd4558e82c05b0d (patch) | |
tree | 7d5096febe4f2b3af4d0d24e9d1a12bb904d9e2a /src/arch/arm/isa.hh | |
parent | 896c7617c47cd83b0e119b62baa133307d05cecd (diff) | |
download | gem5-e658b6fed46afb0b587dba037bd4558e82c05b0d.tar.xz |
ARM: Add support for the clidr register.
This register will always report 0 caches as implemented. It's not clear how
to find out how many there really are when dealing with an arbitrary
hierarchy.
Diffstat (limited to 'src/arch/arm/isa.hh')
-rw-r--r-- | src/arch/arm/isa.hh | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index dd80976bb..1d8f14cab 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -164,6 +164,11 @@ namespace ArmISA panic("Unimplemented CP15 register %s read.\n", miscRegName[misc_reg]); } + switch (misc_reg) { + case MISCREG_CLIDR: + warn("The clidr register always reports 0 caches.\n"); + break; + } return readMiscRegNoEffect(misc_reg); } |