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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-22 15:50:16 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-03-23 10:24:24 +0000 |
| commit | 33bb1aa386fd6e6b4bc93797e129bc5c4baa6a36 (patch) | |
| tree | ea5442af324c3dbb5affee093c8dd6b97e00b291 /src/arch/arm/isa.hh | |
| parent | e09a581188cbc2e1ff989d500399d0125a4dbc07 (diff) | |
| download | gem5-33bb1aa386fd6e6b4bc93797e129bc5c4baa6a36.tar.xz | |
arch-arm: Created function for TLB ASID Invalidation
This patch is intended to avoid code duplication and extends the set of
TLBI ISA functions adding the entry invalidation by ASID match.
Change-Id: I9bcb498059ea480dd2118639c7b3c64fea80a5e1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9181
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa.hh')
| -rw-r--r-- | src/arch/arm/isa.hh | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index f36bc89ca..05d118c4d 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -404,6 +404,9 @@ namespace ArmISA void tlbiIPA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, uint8_t target_el); + void tlbiASID(ThreadContext *tc, uint16_t asid, bool secure_lookup, + uint8_t target_el); + public: void clear(); void clear64(const ArmISAParams *p); |