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| author | Jordi Vaquero <jordi.vaquero@metempsy.com> | 2019-08-06 15:49:14 +0200 |
|---|---|---|
| committer | Jordi Vaquero <jordi.vaquero@metempsy.com> | 2019-08-07 14:30:51 +0000 |
| commit | 92abad849186256f4a4b309ed867d375d07c5c63 (patch) | |
| tree | 757b4fb7225fe35d8739ad2950aaa51042a362f2 /src/arch/arm/isa.hh | |
| parent | 676d5fe4e882c9d073964a72c619024306fd279a (diff) | |
| download | gem5-92abad849186256f4a4b309ed867d375d07c5c63.tar.xz | |
arch-arm: adding register control flags enabling LSE implementation
Added changes on arch-arm architecture to accept Atomic instructions
following ARM v8.1 documentation. That includes enabling atomic bit
in ID registers and add have_lse variable into arm system.
Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19809
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/isa.hh')
| -rw-r--r-- | src/arch/arm/isa.hh | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 63051cd83..5e337c223 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -95,6 +95,7 @@ namespace ArmISA bool haveGICv3CPUInterface; uint8_t physAddrRange; bool haveSVE; + bool haveLSE; bool havePAN; /** SVE vector length in quadwords */ @@ -687,6 +688,7 @@ namespace ArmISA SERIALIZE_SCALAR(physAddrRange); SERIALIZE_SCALAR(haveSVE); SERIALIZE_SCALAR(sveVL); + SERIALIZE_SCALAR(haveLSE); SERIALIZE_SCALAR(havePAN); } void unserialize(CheckpointIn &cp) @@ -704,6 +706,7 @@ namespace ArmISA UNSERIALIZE_SCALAR(physAddrRange); UNSERIALIZE_SCALAR(haveSVE); UNSERIALIZE_SCALAR(sveVL); + UNSERIALIZE_SCALAR(haveLSE); UNSERIALIZE_SCALAR(havePAN); } |