diff options
| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2017-10-13 10:03:14 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-11-15 14:11:44 +0000 |
| commit | ef0490081fa7ebcda2e1c7adccb05b3a14014cf1 (patch) | |
| tree | 8073449559fecaf9bc1fb8f280a50a30a9313863 /src/arch/arm/isa/decoder | |
| parent | f0f04ddd70aa3260f5282227de264653ac36fabe (diff) | |
| download | gem5-ef0490081fa7ebcda2e1c7adccb05b3a14014cf1.tar.xz | |
arm: Add support for armv8 CRC32 instructions
This patch introduces the ARM A32/T32/A64 CRC Instructions, which are
mandatory since ARMv8.1. The UNPREDICTABLE behaviours are implemented as
follows:
1) CRC32(C)X (64 bit) instructions are decoded as Undefined in Aarch32
2) The instructions support predication in Aarch32
3) Using R15(PC) as source/dest operand is permitted in Aarch32
Change-Id: Iaf29b05874e1370c7615da79a07f111ded17b6cc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5521
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/decoder')
| -rw-r--r-- | src/arch/arm/isa/decoder/arm.isa | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa index f0c0dec18..9b8b37a9c 100644 --- a/src/arch/arm/isa/decoder/arm.isa +++ b/src/arch/arm/isa/decoder/arm.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010-2013 ARM Limited +// Copyright (c) 2010-2013,2017 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -72,6 +72,7 @@ format DataOp { 0x3: decode OPCODE { 0x9: ArmBlxReg::armBlxReg(); } + 0x4: Crc32::crc32(); 0x5: ArmSatAddSub::armSatAddSub(); 0x6: ArmERet::armERet(); 0x7: decode OPCODE_22 { |