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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:05 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:05 -0500 |
| commit | cbdebf852efd56651a18532c6ffbe7ac580aa539 (patch) | |
| tree | b54a69ff77cb04a876835f6033a3635d495aa458 /src/arch/arm/isa/decoder | |
| parent | caa95639ec2fe7cd45edf679d5fbf6b7a7072fb3 (diff) | |
| download | gem5-cbdebf852efd56651a18532c6ffbe7ac580aa539.tar.xz | |
ARM: Implement SVC (was SWI) outside of the decoder.
Diffstat (limited to 'src/arch/arm/isa/decoder')
| -rw-r--r-- | src/arch/arm/isa/decoder/arm.isa | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa index fe7e67b11..58b9f6699 100644 --- a/src/arch/arm/isa/decoder/arm.isa +++ b/src/arch/arm/isa/decoder/arm.isa @@ -286,13 +286,7 @@ format DataOp { } // CPNUM (OP4 == 1) } //OPCODE_4 - 1: PredOp::swi({{ -#if FULL_SYSTEM - fault = new SupervisorCall(); -#else - fault = new SupervisorCall(machInst); -#endif - }}, IsSyscall); + 1: Svc::svc(); } // OPCODE_24 } |