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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-18 17:14:56 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-23 14:08:55 +0000 |
| commit | 51aba755390f96a7f1d997b1849bd47072823dea (patch) | |
| tree | ef44039597cb235602b4a6bd0834f70aace41f57 /src/arch/arm/isa/formats/mem.isa | |
| parent | e1ef0270da9626bd45f4ad1375c9a3d8bccd6fa7 (diff) | |
| download | gem5-51aba755390f96a7f1d997b1849bd47072823dea.tar.xz | |
arch-arm: Remove SWP and SWPB instructions
The SWP and SWPB instructions have been removed from AArch32. It was
previously (ARMv7) possible to enable them with the ID_ISAR0.Swap bits,
which are now hardcoded to 0b0000 (SWP and SWPB not implemented)
Change-Id: Ic32b534454a7e0f7494a6f0b5e11182c65b3fe24
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15815
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/formats/mem.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/mem.isa | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa index 50e3e358f..888bbdff6 100644 --- a/src/arch/arm/isa/formats/mem.isa +++ b/src/arch/arm/isa/formats/mem.isa @@ -226,10 +226,6 @@ def format ArmSyncMem() {{ const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); switch (PUBWL) { - case 0x10: - return new Swp(machInst, rt, rt2, rn); - case 0x14: - return new Swpb(machInst, rt, rt2, rn); case 0x18: return new %(strex)s(machInst, rt, rt2, rn, true, 0); case 0x19: |