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path: root/src/arch/arm/isa/formats/mem.isa
AgeCommit message (Expand)Author
2019-01-23arch-arm: Implement LoadAcquire/StoreRelease in AArch32Giacomo Travaglini
2019-01-23arch-arm: Remove SWP and SWPB instructionsGiacomo Travaglini
2018-06-22arch-arm: BadMode checking if corresponding EL is implementedGiacomo Travaglini
2018-03-15arm: Fix implicit-fallthrough warnings when building with gcc-7+Siddhesh Poyarekar
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
2010-07-15ARM: Make an SRS instruction with a bad mode cause an undefined instruction f...Gabe Black
2010-06-02ARM: Treat LDRD in ARM with an odd index as an undefined instruction.Gabe Black
2010-06-02ARM: Decode the SRS instruction.Gabe Black
2010-06-02ARM: Decode TBB and TBH.Gabe Black
2010-06-02ARM: Decode the arm version of ldrexd.Gabe Black
2010-06-02ARM: Decode the strex instructions.Gabe Black
2010-06-02ARM: Decode the RFE instruction.Gabe Black
2010-06-02ARM: Make sure some undefined thumb32 instructions fault.Gabe Black
2010-06-02ARM: Decode the thumb version of the ldrd and strd instructions.Gabe Black
2010-06-02ARM: Explicitly keep track of the second destination for double loads/stores.Gabe Black
2010-06-02ARM: Decode the thumb32 load byte/memory hint instructions.Gabe Black
2010-06-02ARM: Decode the load halfword, memory hints instructions for 32 bit Thumb.Gabe Black
2010-06-02ARM: Decode the ldrex instruction.Gabe Black
2010-06-02ARM: Rearrange the load/store double/exclusive, table branch thumb decoding.Gabe Black
2010-06-02ARM: Decode the swp and swpb instructions.Gabe Black
2010-06-02ARM: Eliminate the old memory formats which are no longer used.Gabe Black
2010-06-02ARM: Make the addressing mode 3 loads/stores use the externally defined instr...Gabe Black
2010-06-02ARM: Decode 16 bit thumb PC relative memory instructions.Gabe Black
2010-06-02ARM: Decode 16 bit thumb immediate addressed memory instructions.Gabe Black
2010-06-02ARM: Decode 16 bit thumb register addressed memory instructions.Gabe Black
2010-06-02ARM: Make single stores decode to the new external store instructions.Gabe Black
2010-06-02ARM: Make 32 bit thumb use the new, external load instructions.Gabe Black
2010-06-02ARM: Define the store instructions from outside the decoder.Gabe Black
2010-06-02ARM: Define the load instructions from outside the decoder.Gabe Black
2010-03-23cpu: fix exec tracing memory corruption bugSteve Reinhardt
2009-07-08ARM: Improve memory instruction disassembly.Gabe Black
2009-07-08ARM: Get rid of the MemAcc and EAComp static insts.Gabe Black
2009-07-08ARM: Add an AddrMode2 format for memory instructions that use address mode 2.Gabe Black
2009-07-08ARM: Don't always update CPSR.Gabe Black
2009-07-08ARM: Add an AddrMode3 format for memory instructions that use address mode 3.Gabe Black
2009-06-21ARM: Simplify the ISA desc by pulling some classes out of it.Gabe Black
2009-06-21ARM: Don't downconvert ExtMachInsts to MachInsts.Gabe Black
2009-06-21ARM: Get rid of unnecessary fp_enable_checks.Gabe Black
2009-06-21ARM: Make the isa parser aware that CPSR is being used.Gabe Black
2009-06-21ARM: Pull some static code out of the isa desc and create miscregs.hh.Gabe Black
2009-06-21ARM: Get rid of unused postacc_code.Gabe Black
2009-04-05arm: add ARM support to M5Stephen Hines