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author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:10 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:10 -0500 |
commit | 6fb5189c47546fe97fb66550f5484f4d96c4397b (patch) | |
tree | a21e47d2384de03a03bc6140db689c9c551ccbb9 /src/arch/arm/isa/formats/misc.isa | |
parent | 89b1dd558278546a3042296d1b6c43c64d63a87e (diff) | |
download | gem5-6fb5189c47546fe97fb66550f5484f4d96c4397b.tar.xz |
ARM: Ignore/warn on accesses to the DRBAR, DRACR, and DRSR registers.
Diffstat (limited to 'src/arch/arm/isa/formats/misc.isa')
-rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 8d386b0b0..d01b5014d 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -128,6 +128,15 @@ def format McrMrc15() {{ case MISCREG_BPIALL: return new WarnUnimplemented( isRead ? "mrc bpiall" : "mcr bpiall", machInst); + case MISCREG_DRBAR: + return new WarnUnimplemented( + isRead ? "mrc drbar" : "mcr drbar", machInst); + case MISCREG_DRACR: + return new WarnUnimplemented( + isRead ? "mrc dracr" : "mcr dracr", machInst); + case MISCREG_DRSR: + return new WarnUnimplemented( + isRead ? "mrc drsr" : "mcr drsr", machInst); default: if (isRead) { return new Mrc15(machInst, rt, (IntRegIndex)miscReg); |