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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:18:24 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:18:24 -0500 |
| commit | 9900629f83139ed213a440375ea32bc95333b8d9 (patch) | |
| tree | 1cfe6a9e6f854d8f48c5bb1aa863b8c9c7db838a /src/arch/arm/isa/formats/misc.isa | |
| parent | e3ee27c7b4da421676ca7d77c0953726259890d5 (diff) | |
| download | gem5-9900629f83139ed213a440375ea32bc95333b8d9.tar.xz | |
arm: Mark some miscregs (timer counter) registers at unverifiable.
The checker can't verify timer registers, so it should just grab the version
from the executing CPU, otherwise it could get a larger value and diverge
execution.
Diffstat (limited to 'src/arch/arm/isa/formats/misc.isa')
| -rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 925ed55cd..f81b96f2f 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -273,8 +273,12 @@ let {{ if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) { uint32_t iss = mcrrMrrcIssBuild(isRead, crm, rt, rt2, opc1); - if (isRead) - return new Mrrc15(machInst, miscReg, rt2, rt, iss); + if (isRead) { + StaticInstPtr si = new Mrrc15(machInst, miscReg, rt2, rt, iss); + if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE]) + si->setFlag(StaticInst::IsUnverifiable); + return si; + } return new Mcrr15(machInst, rt2, rt, miscReg, iss); } else { return new FailUnimplemented(isRead ? "mrrc" : "mcrr", machInst, |