diff options
| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-08-29 09:26:35 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-09-06 20:00:34 +0000 |
| commit | 982a7d4f13e8919cd50dccc29d001f1e98fc2fbb (patch) | |
| tree | 576b0c661ee594b1f77e7f272d878e12652b460c /src/arch/arm/isa/insts/data64.isa | |
| parent | 2d2f51f9897059cea36329aea20a585e0308ccad (diff) | |
| download | gem5-982a7d4f13e8919cd50dccc29d001f1e98fc2fbb.tar.xz | |
arch-arm: Add explicit AArch64 MiscReg banking
Change-Id: I89836d14491a51b1573f45c8012e3ad12b107d24
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20623
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/isa/insts/data64.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/data64.isa | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa index a2ffb9f5a..f5be4763a 100644 --- a/src/arch/arm/isa/insts/data64.isa +++ b/src/arch/arm/isa/insts/data64.isa @@ -331,16 +331,18 @@ let {{ ''' msr_check_code = ''' + auto pre_flat = (MiscRegIndex)snsBankedIndex64(dest, xc->tcBase()); MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()-> - flattenRegId(RegId(MiscRegClass, dest)).index(); + flattenRegId(RegId(MiscRegClass, pre_flat)).index(); CPSR cpsr = Cpsr; ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; %s ''' % (msrMrs64EnabledCheckCode % ('Write'),) mrs_check_code = ''' + auto pre_flat = (MiscRegIndex)snsBankedIndex64(op1, xc->tcBase()); MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()-> - flattenRegId(RegId(MiscRegClass, op1)).index(); + flattenRegId(RegId(MiscRegClass, pre_flat)).index(); CPSR cpsr = Cpsr; ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; %s @@ -509,8 +511,10 @@ let {{ def buildMsrImmInst(mnem, inst_name, code): global header_output, decoder_output, exec_output msrImmPermission = ''' - auto misc_index = (MiscRegIndex) xc->tcBase()->flattenRegId( - RegId(MiscRegClass, dest)).index(); + auto pre_flat = + (MiscRegIndex)snsBankedIndex64(dest, xc->tcBase()); + MiscRegIndex misc_index = (MiscRegIndex) xc->tcBase()-> + flattenRegId(RegId(MiscRegClass, pre_flat)).index(); if (!miscRegInfo[misc_index][MISCREG_IMPLEMENTED]) { return std::make_shared<UndefinedInstruction>( |