gem5 - gem5

Age	Commit message (Expand)	Author
2020-02-04	arch-arm: AArch64 reg access HCR_EL2.E2H filter	Adrian Herrera
2019-11-05	arch-arm: Annotate original address in CMOs	Giacomo Travaglini
2019-10-03	arch-arm: Annotate CM flag in AA64 CM Instructions	Giacomo Travaglini
2019-09-06	arch-arm: Add explicit AArch64 MiscReg banking	Giacomo Travaglini
2019-09-06	arch-arm: Use same template across all MSR inst	Giacomo Travaglini
2019-08-05	arch-arm: Implement ARMv8.1-PAN, Privileged access never	Giacomo Travaglini
2019-08-05	arch-arm: Rewrite MSR immediate instruction class	Giacomo Travaglini
2018-10-26	arch-arm: Refactor AArch64 MSR/MRS trapping	Giacomo Travaglini
2018-10-26	arch-arm: Trap to EL2 only if not in Secure State	Giacomo Travaglini
2018-02-07	arch-arm: Change the type of fault for dc ivac instructions	Nikos Nikoleris
2018-02-07	arch-arm: Unify permission checks for dc * instructions	Nikos Nikoleris
2018-02-07	arch-arm: Turn dc ivac to dc civac when some conditions are met	Nikos Nikoleris
2018-02-07	arch-arm: Fix printing of the data cache maintenance instructions	Nikos Nikoleris
2017-12-05	arm: Add support for the dc {civac, cvac, cvau, ivac} instr	Nikos Nikoleris
2017-11-21	arch-arm: Fix MSR/MRS disassemble	Giacomo Travaglini
2017-11-15	arm: Add support for armv8 CRC32 instructions	Giacomo Travaglini
2017-10-20	arch-arm: RBIT instruction using mirroring func	Giacomo Travaglini
2017-07-05	cpu: Simplify the rename interface and use RegId	Rekai Gonzalez-Alberquilla
2017-02-21	arm: Fix DPRINTFs with arguments in the instruction declarations	Nikos Nikoleris
2016-08-02	arm: Fix trapping to Hypervisor during MSR/MRS read/write	Dylan Johnson
2014-10-16	arch: Use shared_ptr for all Faults	Andreas Hansson
2014-04-17	arm: Make sure UndefinedInstructions are properly initialized	Ali Saidi
2014-01-24	arm: Add support for ARMv8 (AArch64 & AArch32)	ARM gem5 Developers