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| author | Adrian Herrera <adrian.herrera@arm.com> | 2019-11-07 12:30:08 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2020-02-04 13:39:54 +0000 |
| commit | 98b2d7acc57b664996de528e6d32ae8abaee2b99 (patch) | |
| tree | 21d2559d24dd6506bbfd29819115d1500f9b0b6a /src/arch/arm/isa/insts/data64.isa | |
| parent | 465f7d0f56fe47ad5070cc7fcc69bf69cb7d3d82 (diff) | |
| download | gem5-98b2d7acc57b664996de528e6d32ae8abaee2b99.tar.xz | |
arch-arm: AArch64 reg access HCR_EL2.E2H filter
Some AArch64 system registers report UNDEFINED behaviours if accessed
from EL2 or EL3 in a non-EL2 Host enabled (HCR_EL2.E2H == 0) environment.
Examples of these are seen in the Generic Timer system registers,
namely CNTP_CTL_EL02 or CNTKCTL_EL12.
This patch provides an ISA filter for specifying the above condition.
Change-Id: I240f9afdb000faf5d3c9274ba12bd4cc41fe8604
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24664
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/isa/insts/data64.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/data64.isa | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa index 75d47925f..65ca024e9 100644 --- a/src/arch/arm/isa/insts/data64.isa +++ b/src/arch/arm/isa/insts/data64.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2011-2013, 2016-2019 ARM Limited +// Copyright (c) 2011-2013, 2016-2020 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -313,7 +313,7 @@ let {{ msrMrs64EnabledCheckCode = ''' // Check for read/write access right - if (!can%sAArch64SysReg(flat_idx, Scr64, cpsr, xc->tcBase())) { + if (!can%sAArch64SysReg(flat_idx, Hcr64, Scr64, cpsr, xc->tcBase())) { if (flat_idx == MISCREG_DAIF || flat_idx == MISCREG_DC_ZVA_Xt || flat_idx == MISCREG_DC_CVAC_Xt || @@ -537,7 +537,7 @@ let {{ mnemonic); } - if (!canWriteAArch64SysReg(misc_index, + if (!canWriteAArch64SysReg(misc_index, Hcr64, Scr64, Cpsr, xc->tcBase())) { return std::make_shared<UndefinedInstruction>( |