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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-09-12 10:23:16 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-10-03 09:05:19 +0000 |
| commit | d9fee95b715e54eafbd2c5c2a618ef92af32e3a5 (patch) | |
| tree | 7986134faa96a3cc130c84135a06afc3c2d28e6d /src/arch/arm/isa/insts/data64.isa | |
| parent | acd148a76c29a6e647dc2cc15ef17667c61f8de6 (diff) | |
| download | gem5-d9fee95b715e54eafbd2c5c2a618ef92af32e3a5.tar.xz | |
arch-arm: Annotate CM flag in AA64 CM Instructions
DC ZVA instruction is not classified as a cache maintenance instruction,
and therefore its execution cannot cause this field to be set to 1.
Change-Id: I0f30db1e6fc629dc52293edfb2bac4cf99ee49cc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21306
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/insts/data64.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/data64.isa | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa index f5be4763a..fcce0112a 100644 --- a/src/arch/arm/isa/insts/data64.isa +++ b/src/arch/arm/isa/insts/data64.isa @@ -410,6 +410,12 @@ let {{ exec_output += DCStore64InitiateAcc.subst(msrDCZVAIop); exec_output += Store64CompleteAcc.subst(msrDCZVAIop); + # Cache maintenance fault annotation + # The DC ZVA instruction is not classified as a cache maintenance + # instruction, and therefore we shouldn't annotate it + cachem_fa = ''' + fault->annotate(ArmFault::CM, 1); + ''' msrdccvau_ea_code = msr_check_code msrdccvau_ea_code += ''' @@ -425,7 +431,8 @@ let {{ { "ea_code" : msrdccvau_ea_code, "memacc_code" : ';', "use_uops" : 0, - "op_wb" : ";", "fa_code" : ";"}, + "op_wb" : ";", + "fa_code" : cachem_fa}, ['IsStore', 'IsMemRef']); header_output += DCStore64Declare.subst(msrDCCVAUIop); decoder_output += DCStore64Constructor.subst(msrDCCVAUIop); @@ -448,7 +455,8 @@ let {{ { "ea_code" : msrdccvac_ea_code, "memacc_code" : ';', "use_uops" : 0, - "op_wb" : ";", "fa_code" : ";"}, + "op_wb" : ";", + "fa_code" : cachem_fa}, ['IsStore', 'IsMemRef']); header_output += DCStore64Declare.subst(msrDCCVACIop); decoder_output += DCStore64Constructor.subst(msrDCCVACIop); @@ -471,7 +479,8 @@ let {{ { "ea_code" : msrdccivac_ea_code, "memacc_code" : ';', "use_uops" : 0, - "op_wb" : ";", "fa_code" : ";"}, + "op_wb" : ";", + "fa_code" : cachem_fa}, ['IsStore', 'IsMemRef']); header_output += DCStore64Declare.subst(msrDCCIVACIop); decoder_output += DCStore64Constructor.subst(msrDCCIVACIop); @@ -500,7 +509,8 @@ let {{ { "ea_code" : msrdcivac_ea_code, "memacc_code" : ';', "use_uops" : 0, - "op_wb" : ";", "fa_code" : ";"}, + "op_wb" : ";", + "fa_code" : cachem_fa}, ['IsStore', 'IsMemRef']); header_output += DCStore64Declare.subst(msrDCIVACIop); decoder_output += DCStore64Constructor.subst(msrDCIVACIop); |