arch-arm: Rewrite MSR immediate instruction class

MSR <pstatefield>, #imm is used for setting a PSTATE field using an
immediate. Current implementation has the following flaws:

* There is no base MSR immediate definition: all the existing
PSTATE fields have a different class definition
* Those implementation make use of a generic data64 base class
which results in a wrong disassembly (pstate register is printed as an
integer register).

This patch is fixing this by defining a new base class (MiscRegImmOp64)
and new related templates. In this way, we aim to ease addition of new
PSTATE fields (in ARMv8.x)

Change-Id: I71b630ff32abe1b105bbb3ab5781c6589b67d419
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19728
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

1 files changed, 31 insertions, 33 deletions

diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa
index d348190ae..b3e03d67d 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2011-2013, 2016-2018 ARM Limited
+// Copyright (c) 2011-2013, 2016-2019 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -509,45 +509,43 @@ let {{
     exec_output += DCStore64InitiateAcc.subst(msrDCIVACIop);
     exec_output += Store64CompleteAcc.subst(msrDCIVACIop);
 
+    def buildMsrImmInst(mnem, inst_name, code):
+        global header_output, decoder_output, exec_output
+        msrImmPermission = '''
+            if (!canWriteAArch64SysReg(
+                    (MiscRegIndex) xc->tcBase()->flattenRegId(
+                       RegId(MiscRegClass, dest)).index(),
+                    Scr64, Cpsr, xc->tcBase())) {
+                return std::make_shared<UndefinedInstruction>(
+                                machInst, 0, EC_TRAPPED_MSR_MRS_64,
+                                mnemonic);
+            }
 
-    buildDataXImmInst("msrSP", '''
-        if (!canWriteAArch64SysReg(
-                (MiscRegIndex) xc->tcBase()->flattenRegId(
-                   RegId(MiscRegClass, dest)).index(),
-                Scr64, Cpsr, xc->tcBase())) {
-            return std::make_shared<UndefinedInstruction>(machInst, false,
-                                                          mnemonic);
-        }
-        MiscDest_ud = imm;
-    ''', optArgs = ["IsSerializeAfter", "IsNonSpeculative"])
-
-    buildDataXImmInst("msrDAIFSet", '''
-        if (!canWriteAArch64SysReg(
-                (MiscRegIndex) xc->tcBase()->flattenRegId(
-                   RegId(MiscRegClass, dest)).index(),
-                Scr64, Cpsr, xc->tcBase())) {
-            return std::make_shared<UndefinedInstruction>(
-                            machInst, 0, EC_TRAPPED_MSR_MRS_64,
-                            mnemonic);
-        }
+        '''
+        msrIop = InstObjParams("msr", inst_name, "MiscRegImmOp64",
+                               msrImmPermission + code,
+                               ["IsSerializeAfter", "IsNonSpeculative"])
+        header_output += MiscRegOp64Declare.subst(msrIop)
+        decoder_output += MiscRegOp64Constructor.subst(msrIop)
+        exec_output += BasicExecute.subst(msrIop)
+
+    buildMsrImmInst("msr", "MsrImm64", '''
+        // Mask and shift immediate (depending on PSTATE field)
+        // before assignment
+        MiscDest_ud = miscRegImm();
+    ''')
+
+    buildMsrImmInst("msr", "MsrImmDAIFSet64", '''
         CPSR cpsr = Cpsr;
         cpsr.daif = cpsr.daif | imm;
         Cpsr = cpsr;
-    ''', optArgs = ["IsSerializeAfter", "IsNonSpeculative"])
-
-    buildDataXImmInst("msrDAIFClr", '''
-        if (!canWriteAArch64SysReg(
-                (MiscRegIndex) xc->tcBase()->flattenRegId(
-                   RegId(MiscRegClass, dest)).index(),
-                Scr64, Cpsr, xc->tcBase())) {
-            return std::make_shared<UndefinedInstruction>(
-                                machInst, 0, EC_TRAPPED_MSR_MRS_64,
-                                mnemonic);
-        }
+    ''')
+
+    buildMsrImmInst("msr", "MsrImmDAIFClr64", '''
         CPSR cpsr = Cpsr;
         cpsr.daif = cpsr.daif & ~imm;
         Cpsr = cpsr;
-    ''', optArgs = ["IsSerializeAfter", "IsNonSpeculative"])
+    ''')
 
     def buildDataXCompInst(mnem, instType, suffix, code):
         global header_output, decoder_output, exec_output