diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
---|---|---|
committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
commit | 401165c778108ab22aeeee55c4f4451ca93bcffb (patch) | |
tree | f525ba64108f6ebe208a04d2dee7b77621cafd96 /src/arch/arm/isa/insts/fp.isa | |
parent | e097c4fb188fafc9cd2253500ab2d056da886c9c (diff) | |
download | gem5-401165c778108ab22aeeee55c4f4451ca93bcffb.tar.xz |
ARM: Further break up condition code into NZ, C, V bits.
Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.
Diffstat (limited to 'src/arch/arm/isa/insts/fp.isa')
-rw-r--r-- | src/arch/arm/isa/insts/fp.isa | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa index 53d0b3413..73b3aa50e 100644 --- a/src/arch/arm/isa/insts/fp.isa +++ b/src/arch/arm/isa/insts/fp.isa @@ -235,16 +235,18 @@ let {{ decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop); exec_output += PredOpExecute.subst(vmrsFpscrIop); - vmrsApsrFpscrCode = vmrsEnabledCheckCode + ''' - Dest = FpCondCodes & FpCondCodesMask; + vmrsApsrFpscrCode = vmrsApsrEnabledCheckCode + ''' + FPSCR fpscr = FpCondCodes; + CondCodesNZ = (fpscr.n << 1) | fpscr.z; + CondCodesC = fpscr.c; + CondCodesV = fpscr.v; ''' - vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "FpRegRegImmOp", + vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "PredOp", { "code": vmrsApsrFpscrCode, "predicate_test": predicateTest, - "op_class": "SimdFloatMiscOp" }, - ["IsSerializeBefore"]) - header_output += FpRegRegImmOpDeclare.subst(vmrsApsrFpscrIop); - decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrFpscrIop); + "op_class": "SimdFloatMiscOp" }) + header_output += BasicDeclare.subst(vmrsApsrFpscrIop); + decoder_output += BasicConstructor.subst(vmrsApsrFpscrIop); exec_output += PredOpExecute.subst(vmrsApsrFpscrIop); vmovImmSCode = vfpEnabledCheckCode + ''' |