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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
| commit | 401165c778108ab22aeeee55c4f4451ca93bcffb (patch) | |
| tree | f525ba64108f6ebe208a04d2dee7b77621cafd96 /src/arch/arm/isa/insts/mult.isa | |
| parent | e097c4fb188fafc9cd2253500ab2d056da886c9c (diff) | |
| download | gem5-401165c778108ab22aeeee55c4f4451ca93bcffb.tar.xz | |
ARM: Further break up condition code into NZ, C, V bits.
Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.
Diffstat (limited to 'src/arch/arm/isa/insts/mult.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/mult.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/mult.isa b/src/arch/arm/isa/insts/mult.isa index 31febe747..f4f8b867e 100644 --- a/src/arch/arm/isa/insts/mult.isa +++ b/src/arch/arm/isa/insts/mult.isa @@ -52,7 +52,7 @@ let {{ _in = (resTemp >> %(negBit)d) & 1; _iz = ((%(zType)s)resTemp == 0); - CondCodesF = _in << 31 | _iz << 30 | (CondCodesF & 0x3FFFFFFF); + CondCodesNZ = (_in << 1) | _iz; DPRINTF(Arm, "(in, iz) = (%%d, %%d)\\n", _in, _iz); ''' |