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| author | Ali Saidi <ali.saidi@arm.com> | 2010-08-25 19:10:42 -0500 |
|---|---|---|
| committer | Ali Saidi <ali.saidi@arm.com> | 2010-08-25 19:10:42 -0500 |
| commit | 99fafb72b87f3b63f205bee7b20b8c19724d6305 (patch) | |
| tree | 305127cadcae96140871d128525bc89c5a1486ec /src/arch/arm/isa/insts/neon.isa | |
| parent | 63464d950ec4e8b8f3aa86802ca9fbf1e8c662b6 (diff) | |
| download | gem5-99fafb72b87f3b63f205bee7b20b8c19724d6305.tar.xz | |
ARM: Fix VFP enabled checks for mem instructions
Diffstat (limited to 'src/arch/arm/isa/insts/neon.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/neon.isa | 9 |
1 files changed, 1 insertions, 8 deletions
diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa index 790c9c3a1..0a3285490 100644 --- a/src/arch/arm/isa/insts/neon.isa +++ b/src/arch/arm/isa/insts/neon.isa @@ -620,13 +620,6 @@ output exec {{ }}; let {{ - simdEnabledCheckCode = ''' - if (!neonEnabled(Cpacr, Cpsr, Fpexc)) - return disabledFault(); - ''' -}}; - -let {{ header_output = "" exec_output = "" @@ -3235,7 +3228,7 @@ let {{ RegVect srcReg1, srcReg2, destReg; ''' for reg in range(rCount): - eWalkCode += ''' + eWalkCode += simdEnabledCheckCode + ''' srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw); srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw); ''' % { "reg" : reg } |