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| author | Edmund Grimley Evans <Edmund.Grimley-Evans@arm.com> | 2018-06-28 14:32:01 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2018-10-02 14:10:50 +0000 |
| commit | 352d666fa1e9b5ae960127c95d19cf63c8ff0df7 (patch) | |
| tree | 60fe09123ff1da0192b53fd36a6623d880b5509c /src/arch/arm/isa/insts/neon64.isa | |
| parent | 9c687a6f70a7b88b8e8c125421c5f5e765b928a5 (diff) | |
| download | gem5-352d666fa1e9b5ae960127c95d19cf63c8ff0df7.tar.xz | |
arch-arm: Add FP16 support introduced by Armv8.2-A
This changeset adds support for FP/SIMD instructions with
half-precision floating-point operands.
Change-Id: I4957f111c9c5e5d6a3747fe9d169d394d642fee8
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/13084
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/insts/neon64.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/neon64.isa | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/isa/insts/neon64.isa b/src/arch/arm/isa/insts/neon64.isa index 4897e7c91..eb130dbbd 100644 --- a/src/arch/arm/isa/insts/neon64.isa +++ b/src/arch/arm/isa/insts/neon64.isa @@ -1,6 +1,6 @@ // -*- mode: c++ -*- -// Copyright (c) 2012-2013, 2015-2016 ARM Limited +// Copyright (c) 2012-2013, 2015-2018 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -45,7 +45,7 @@ let {{ decoders = { 'Generic' : {} } # FP types (FP operations always work with unsigned representations) - floatTypes = ("uint32_t", "uint64_t") + floatTypes = ("uint16_t", "uint32_t", "uint64_t") smallFloatTypes = ("uint32_t",) def threeEqualRegInstX(name, Name, opClass, types, rCount, op, |