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| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-05-09 18:58:47 -0400 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-05-09 18:58:47 -0400 |
| commit | af39ab297f7c666e77d29e836a4ff4c2a6d672a9 (patch) | |
| tree | 519bce2e113e54ce6b2165d92fd1436e45200dd8 /src/arch/arm/isa/insts/neon64.isa | |
| parent | fe27f937aa833a2d25e0462fd0cac301a45df8cb (diff) | |
| download | gem5-af39ab297f7c666e77d29e836a4ff4c2a6d672a9.tar.xz | |
arm: add preliminary ISA splits for ARM arch
Diffstat (limited to 'src/arch/arm/isa/insts/neon64.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/neon64.isa | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/neon64.isa b/src/arch/arm/isa/insts/neon64.isa index e065761f4..bbe57bdfa 100644 --- a/src/arch/arm/isa/insts/neon64.isa +++ b/src/arch/arm/isa/insts/neon64.isa @@ -1959,6 +1959,9 @@ let {{ 2, minAcrossCode) twoRegAcrossInstX("sminv", "SminvQX", "SimdCmpOp", smallSignedTypes, 4, minAcrossCode) + + split('exec') + # SMLAL, SMLAL2 (by element) mlalCode = "destElem += (BigElement)srcElem1 * (BigElement)srcElem2;" threeRegLongInstX("smlal", "SmlalElemX", "SimdMultAccOp", |