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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:10 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:10 -0500 |
| commit | faf6c727f6f206238eb6cbd4f6c84f6136c739a2 (patch) | |
| tree | b1f0149a9a310b058bcf17d1b03cd5001f1100e2 /src/arch/arm/isa/insts/swap.isa | |
| parent | b6cb6f1874184c72bcf97e7156c5c650be85a7fe (diff) | |
| download | gem5-faf6c727f6f206238eb6cbd4f6c84f6136c739a2.tar.xz | |
ARM: Respect the E bit of the CPSR when doing loads and stores.
Diffstat (limited to 'src/arch/arm/isa/insts/swap.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/swap.isa | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/arch/arm/isa/insts/swap.isa b/src/arch/arm/isa/insts/swap.isa index 9456c1314..29b5b444f 100644 --- a/src/arch/arm/isa/insts/swap.isa +++ b/src/arch/arm/isa/insts/swap.isa @@ -44,7 +44,8 @@ let {{ (newHeader, newDecoder, newExec) = SwapBase("swp", "Swp", "EA = Base;", - "Mem = Op1;", "Dest = memData;", + "Mem = cSwap(Op1.uw, ((CPSR)Cpsr).e);", + "Dest = cSwap((uint32_t)memData, ((CPSR)Cpsr).e);", ["Request::MEM_SWAP", "ArmISA::TLB::AlignWord", "ArmISA::TLB::MustBeOne"], []) @@ -55,7 +56,8 @@ let {{ (newHeader, newDecoder, newExec) = SwapBase("swpb", "Swpb", "EA = Base;", - "Mem.ub = Op1.ub;", "Dest.ub = (uint8_t)memData;", + "Mem.ub = cSwap(Op1.ub, ((CPSR)Cpsr).e);", + "Dest.ub = cSwap((uint8_t)memData, ((CPSR)Cpsr).e);", ["Request::MEM_SWAP", "ArmISA::TLB::AlignByte", "ArmISA::TLB::MustBeOne"], []) |