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| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-06-02 13:38:30 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-06-02 13:38:30 +0100 |
| commit | f48ad5b29d6f291b4f3679ff5fb7b5beae10d6fa (patch) | |
| tree | d08e72f1eeeea81b33b60b6bd0f90f1cbd9f174d /src/arch/arm/isa/insts | |
| parent | 53ae19bb5dce904915385515d87ff3c9a69ee170 (diff) | |
| download | gem5-f48ad5b29d6f291b4f3679ff5fb7b5beae10d6fa.tar.xz | |
arm: Correctly check FP/SIMD access permission in aarch32
The current implementation of aarch32 FP/SIMD in gem5 assumes that EL1
and higher are all 32-bit. This breaks interprocessing since an
aarch64 EL1 uses different enable/disable bits. This change updates
the permission checks to according to what is prescribed by the ARM
ARM.
Change-Id: Icdcef31b00644cfeebec00216b3993aa1de12b88
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
Diffstat (limited to 'src/arch/arm/isa/insts')
| -rw-r--r-- | src/arch/arm/isa/insts/fp.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa index 9a7f3f8a0..34dff5139 100644 --- a/src/arch/arm/isa/insts/fp.isa +++ b/src/arch/arm/isa/insts/fp.isa @@ -260,7 +260,7 @@ let {{ decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop); exec_output += PredOpExecute.subst(vmrsFpscrIop); - vmrsApsrFpscrCode = vmrsApsrEnabledCheckCode + ''' + vmrsApsrFpscrCode = vfpEnabledCheckCode + ''' FPSCR fpscr = FpCondCodes; CondCodesNZ = (fpscr.n << 1) | fpscr.z; CondCodesC = fpscr.c; |