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authorAli Saidi <Ali.Saidi@ARM.com>2014-04-17 16:56:09 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2014-04-17 16:56:09 -0500
commitdbaf43394b23bbe8a3ed617d9f519a328cc8af6e (patch)
tree972b6d9ff782bbbcde313e2a584fd79f73ee1ed7 /src/arch/arm/isa/insts
parenta00b44ebe8dd5fdc47b5b4acbc7507e578b3f1f2 (diff)
downloadgem5-dbaf43394b23bbe8a3ed617d9f519a328cc8af6e.tar.xz
arm: Make sure UndefinedInstructions are properly initialized
Diffstat (limited to 'src/arch/arm/isa/insts')
-rw-r--r--src/arch/arm/isa/insts/data64.isa9
1 files changed, 6 insertions, 3 deletions
diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa
index 77d7541ca..8ec446d16 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -294,7 +294,8 @@ let {{
flat_idx == MISCREG_DC_CVAC_Xt ||
flat_idx == MISCREG_DC_CIVAC_Xt
)
- return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64);
+ return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64,
+ mnemonic);
return new UndefinedInstruction(machInst, false, mnemonic);
}
@@ -396,7 +397,8 @@ let {{
if (!canWriteAArch64SysReg(
(MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest),
Scr64, Cpsr, xc->tcBase())) {
- return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64);
+ return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64,
+ mnemonic);
}
CPSR cpsr = Cpsr;
cpsr.daif = cpsr.daif | imm;
@@ -407,7 +409,8 @@ let {{
if (!canWriteAArch64SysReg(
(MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest),
Scr64, Cpsr, xc->tcBase())) {
- return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64);
+ return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64,
+ mnemonic);
}
CPSR cpsr = Cpsr;
cpsr.daif = cpsr.daif & ~imm;