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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-27 00:53:10 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-27 00:53:10 -0700 |
| commit | 4079792f2b61bd1e7c46a5aa8ddb06974982d1db (patch) | |
| tree | 460f43f9cad7d7ed71e4e6773baa6958d229c5f8 /src/arch/arm/isa/operands.isa | |
| parent | b560acfe17b5898d0c68715f9d1cb7e1dd1f006f (diff) | |
| download | gem5-4079792f2b61bd1e7c46a5aa8ddb06974982d1db.tar.xz | |
ARM: Add in spots for the VFP control registers.
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 6e6eea5a8..ac7427dad 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -82,7 +82,10 @@ def operands {{ 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40), 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 41), - 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 42), - 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 43), + 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', 'IsInteger', 42), + 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', 'IsInteger', 43), + 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', 'IsInteger', 44), + 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 45), + 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 46) }}; |