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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:28 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:28 -0500 |
| commit | ac650199eeb62bf05fec11a4f2d7666cbd31331c (patch) | |
| tree | b1fbf183d0a9ba2fdf28b2d58ded4d8fb7a44c76 /src/arch/arm/isa/operands.isa | |
| parent | be096f91b94ded36f43dd7d547a5671f99a264b1 (diff) | |
| download | gem5-ac650199eeb62bf05fec11a4f2d7666cbd31331c.tar.xz | |
ARM: Fix m5op parameters bug.
All the m5op parameters are 64 bits, but we were only sending 32 bits;
and the static register indexes were incorrectly specified.
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 7b014acd0..20ce6df52 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -149,9 +149,11 @@ def operands {{ 'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'), 'LR': intRegNPC('INTREG_LR'), 'R7': intRegNPC('7'), + # First four arguments are passed in registers 'R0': intRegNPC('0'), - 'R1': intRegNPC('0'), - 'R2': intRegNPC('1'), + 'R1': intRegNPC('1'), + 'R2': intRegNPC('2'), + 'R3': intRegNPC('3'), #Pseudo integer condition code registers 'CondCodes': intRegCC('INTREG_CONDCODES'), |