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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:17 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:17 -0500 |
| commit | 358fdc2a40e8a455f508532b47e55f3252053805 (patch) | |
| tree | 4641a564de6d0ce42a372be77e35cde55e2c177c /src/arch/arm/isa/operands.isa | |
| parent | 596cbe19d4591b900acc022ff5a38fc7ee9a5df7 (diff) | |
| download | gem5-358fdc2a40e8a455f508532b47e55f3252053805.tar.xz | |
ARM: Decode to specialized conditional/unconditional versions of instructions.
This is to avoid condition code based dependences from effectively serializing
instructions when the instruction doesn't actually use them.
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 0c52703e1..a086bb03c 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -154,6 +154,9 @@ def operands {{ 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 2), 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 2), + 'OptCondCodes': ('IntReg', 'uw', + '''(condCode == COND_AL || condCode == COND_UC) ? + INTREG_ZERO : INTREG_CONDCODES''', None, 2), #Register fields for microops 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, maybePCRead, maybePCWrite), |