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author | Gabe Black <gblack@eecs.umich.edu> | 2009-11-08 02:08:40 -0800 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-11-08 02:08:40 -0800 |
commit | 48525f581c6233b8f7a8a872c5774d4e245f431c (patch) | |
tree | d6bfb77abb6e70684f04d21b47731ed7a02bcf94 /src/arch/arm/isa/operands.isa | |
parent | d188821d3700ee42e01fc43c9ef17568991fb3ff (diff) | |
download | gem5-48525f581c6233b8f7a8a872c5774d4e245f431c.tar.xz |
ARM: Split the condition codes out of the CPSR.
This allows those bits to be renamed while allowing the other fields to
control the behavior of the processor.
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
-rw-r--r-- | src/arch/arm/isa/operands.isa | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 4ac6790e5..02acc8ed7 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -66,6 +66,7 @@ def operands {{ 'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7), 'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8), 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9), + 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', 'IsInteger', 10), #Register fields for microops 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite), |