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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:16 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:16 -0500 |
| commit | 05bd3eb4ec3d9fea3dbc46112a47459085d3011c (patch) | |
| tree | 58d50fab58de1e9165bfc28986913811b26b9568 /src/arch/arm/isa/operands.isa | |
| parent | b93ceef5381b7c84b6887b5299ae81ff48ef45c9 (diff) | |
| download | gem5-05bd3eb4ec3d9fea3dbc46112a47459085d3011c.tar.xz | |
ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR.
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 4c269276a..b041cef43 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -171,6 +171,7 @@ def operands {{ 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 2), 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 1), + 'Itstate': ('ControlReg', 'ub', 'MISCREG_ITSTATE', None, 2), 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 2), 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 2), 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 2), |