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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:28 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:28 -0500 |
| commit | a679cd917ac4775979e23594de52f1bca407c08c (patch) | |
| tree | d48bb74b729d2e11e62e1db9a4fb860b70ddd1b3 /src/arch/arm/isa/operands.isa | |
| parent | ac650199eeb62bf05fec11a4f2d7666cbd31331c (diff) | |
| download | gem5-a679cd917ac4775979e23594de52f1bca407c08c.tar.xz | |
ARM: Cleanup implementation of ITSTATE and put important code in PCState.
Consolidate all code to handle ITSTATE in the PCState object rather than
touching a variety of structures/objects.
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 20ce6df52..49a860213 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -217,7 +217,6 @@ def operands {{ #Fixed index control regs 'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr), - 'Itstate': cntrlRegNC('MISCREG_ITSTATE', type = 'ub'), 'Spsr': cntrlRegNC('MISCREG_SPSR'), 'Fpsr': cntrlRegNC('MISCREG_FPSR'), 'Fpsid': cntrlRegNC('MISCREG_FPSID'), @@ -247,7 +246,8 @@ def operands {{ 'Thumb': pcStateReg('thumb', srtPC), 'NextThumb': pcStateReg('nextThumb', srtMode), 'NextJazelle': pcStateReg('nextJazelle', srtMode), - 'ForcedItState': pcStateReg('forcedItState', srtMode), + 'NextItState': pcStateReg('nextItstate', srtMode), + 'Itstate': pcStateReg('itstate', srtMode), #Register operands depending on a field in the instruction encoding. These #should be avoided since they may not be portable across different |