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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-08 13:58:24 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-08 13:58:24 -0600 |
| commit | 432fa0aad6092d6a9252f6a9c83c8b36509c1341 (patch) | |
| tree | 88a01aec1327a2a6046979b7c4b302a7383e6653 /src/arch/arm/isa/operands.isa | |
| parent | 0f2bbe15ddfeb3894726c19e09ed23f7027df1cb (diff) | |
| download | gem5-432fa0aad6092d6a9252f6a9c83c8b36509c1341.tar.xz | |
ARM: Add support for M5 ops in the ARM ISA
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 8e856e74d..3c32d98d1 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -170,6 +170,9 @@ def operands {{ 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 3, maybePCRead, maybePCWrite), 'R7': ('IntReg', 'uw', '7', 'IsInteger', 3), 'R0': ('IntReg', 'uw', '0', 'IsInteger', 3), + 'R1': ('IntReg', 'uw', '0', 'IsInteger', 3), + 'R2': ('IntReg', 'uw', '1', 'IsInteger', 3), + 'Rt' : ('IntReg', 'uw', 'RT', 'IsInteger', 3, maybePCRead, maybePCWrite), 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 3), 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 3), |