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| author | ARM gem5 Developers <none@none> | 2014-01-24 15:29:34 -0600 |
|---|---|---|
| committer | ARM gem5 Developers <none@none> | 2014-01-24 15:29:34 -0600 |
| commit | 612f8f074fa1099cf70faf495d46cc647762a031 (patch) | |
| tree | bd1e99c43bf15292395eadd4b7ae3f5c823545c3 /src/arch/arm/isa_traits.hh | |
| parent | f3585c841e964c98911784a187fc4f081a02a0a6 (diff) | |
| download | gem5-612f8f074fa1099cf70faf495d46cc647762a031.tar.xz | |
arm: Add support for ARMv8 (AArch64 & AArch32)
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.
Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.
Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black
Diffstat (limited to 'src/arch/arm/isa_traits.hh')
| -rw-r--r-- | src/arch/arm/isa_traits.hh | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh index 742ca2037..506c5009c 100644 --- a/src/arch/arm/isa_traits.hh +++ b/src/arch/arm/isa_traits.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010 ARM Limited + * Copyright (c) 2010, 2012 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -95,6 +95,9 @@ namespace ArmISA const Addr PAddrImplMask = (ULL(1) << PABits) - 1; + // Max. physical address range in bits supported by the architecture + const unsigned MaxPhysAddrRange = 48; + // return a no-op instruction... used for instruction fetch faults const ExtMachInst NoopMachInst = 0x01E320F000ULL; @@ -124,6 +127,8 @@ namespace ArmISA INT_IRQ, INT_FIQ, INT_SEV, // Special interrupt for recieving SEV's + INT_VIRT_IRQ, + INT_VIRT_FIQ, NumInterruptTypes }; } // namespace ArmISA |