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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-04-20 09:50:29 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-05-29 10:07:53 +0000 |
| commit | 89b3397cf0daba4b2a339e26183aa82e1a573ad0 (patch) | |
| tree | d578e132772ba806c674e2f452153cc3024801ff /src/arch/arm/miscregs.cc | |
| parent | 2456c917ac654f6b67243c72a47240d22a2bf712 (diff) | |
| download | gem5-89b3397cf0daba4b2a339e26183aa82e1a573ad0.tar.xz | |
arch-arm: Implement ARMv8.1 TTBR1_EL2 register
This patch implements the ARMv8.1 TTBR1_EL2 register, which is used for
getting the translation table base address when a Host Operating System
is running at EL2. (HCR_EL2.E2H = 1)
Change-Id: Ic0ab351cae3fd64855eda7c18c8757da0d7b8663
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10382
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/miscregs.cc')
| -rw-r--r-- | src/arch/arm/miscregs.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 08eb255f3..e1ddbf9d3 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -3535,7 +3535,7 @@ ISA::initializeMiscRegMetadata() .hyp().mon() .mapsTo(MISCREG_HTTBR); InitReg(MISCREG_TTBR1_EL2) - .unimplemented(); + .hyp().mon(); InitReg(MISCREG_TCR_EL2) .hyp().mon() .mapsTo(MISCREG_HTCR); |