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| author | Matt Horsnell <Matt.Horsnell@arm.com> | 2012-03-01 17:26:31 -0600 |
|---|---|---|
| committer | Matt Horsnell <Matt.Horsnell@arm.com> | 2012-03-01 17:26:31 -0600 |
| commit | 08187e3916fa615444ed61d739ac91e284735a66 (patch) | |
| tree | 27e62a6b77e396b2e848ae5d1a2b368e81add490 /src/arch/arm/miscregs.cc | |
| parent | d907d0ec723538c7969bf8f2f2d6f29439b02985 (diff) | |
| download | gem5-08187e3916fa615444ed61d739ac91e284735a66.tar.xz | |
ARM: Add limited CP14 support.
New kernels attempt to read CP14 what debug architecture is available.
These changes add the debug registers and return that none is currently
available.
Diffstat (limited to 'src/arch/arm/miscregs.cc')
| -rw-r--r-- | src/arch/arm/miscregs.cc | 32 |
1 files changed, 31 insertions, 1 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index c31818377..286ecc1de 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010 ARM Limited + * Copyright (c) 2010-2012 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -46,6 +46,36 @@ namespace ArmISA { MiscRegIndex +decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) +{ + switch(crn) { + case 0: + switch (opc2) { + case 0: + switch (crm) { + case 0: + return MISCREG_DBGDIDR; + case 1: + return MISCREG_DBGDSCR_INT; + default: + warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]", + crn, opc1, crm, opc2); + return NUM_MISCREGS; + } + default: + warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]", + crn, opc1, crm, opc2); + return NUM_MISCREGS; + } + default: + warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]", + crn, opc1, crm, opc2); + return NUM_MISCREGS; + } + +} + +MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) { switch (crn) { |