diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-12-19 11:03:27 -0600 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-12-19 11:03:27 -0600 |
| commit | 282cf5807d827d5583e5cd5bffae75c4e5efb116 (patch) | |
| tree | 5a6893f52b49478b3c2fb6214d0eedb73b249b7e /src/arch/arm/miscregs.cc | |
| parent | 9cf6bc444b700bcf8140bb975e99cfdf13c3964c (diff) | |
| download | gem5-282cf5807d827d5583e5cd5bffae75c4e5efb116.tar.xz | |
arm: miscreg refactoring
Change-Id: I4e9e8f264a4a4239dd135a6c7a1c8da213b6d345
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/miscregs.cc')
| -rw-r--r-- | src/arch/arm/miscregs.cc | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index c4915cb54..525d44810 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -2039,12 +2039,8 @@ canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) int flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc) { - int reg_as_int = static_cast<int>(reg); - if (miscRegInfo[reg][MISCREG_BANKED]) { - SCR scr = tc->readMiscReg(MISCREG_SCR); - reg_as_int += (ArmSystem::haveSecurity(tc) && !scr.ns) ? 2 : 1; - } - return reg_as_int; + SCR scr = tc->readMiscReg(MISCREG_SCR); + return flattenMiscRegNsBanked(reg, tc, scr.ns); } int @@ -2052,7 +2048,8 @@ flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns) { int reg_as_int = static_cast<int>(reg); if (miscRegInfo[reg][MISCREG_BANKED]) { - reg_as_int += (ArmSystem::haveSecurity(tc) && !ns) ? 2 : 1; + reg_as_int += (ArmSystem::haveSecurity(tc) && + !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1; } return reg_as_int; } |