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authorGiacomo Travaglini <giacomo.travaglini@arm.com>2018-01-09 10:10:04 +0000
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2018-02-07 15:13:49 +0000
commit7798ffb6948d12c7f2bc63dc9a3263bb19aa3297 (patch)
tree24e2a42dc06b980a86e7763b6b01d9fd7aa372e0 /src/arch/arm/miscregs.cc
parent633fdd5841d8e7798e1b1158261612a6ad84c812 (diff)
downloadgem5-7798ffb6948d12c7f2bc63dc9a3263bb19aa3297.tar.xz
arch-arm: Change function name for banked miscregs
This commit changes the function's name used for retrieving the index of a security banked register given the flatten index. This will avoid confusion with flattenRegId, which has a different purpose. Change-Id: I470ffb55916cb7fc9f78e071a7f2e609c1829f1a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7982 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/miscregs.cc')
-rw-r--r--src/arch/arm/miscregs.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 445ba18cf..a9031fe0e 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -815,14 +815,14 @@ canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
}
int
-flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc)
+snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
{
SCR scr = tc->readMiscReg(MISCREG_SCR);
- return flattenMiscRegNsBanked(reg, tc, scr.ns);
+ return snsBankedIndex(reg, tc, scr.ns);
}
int
-flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns)
+snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
{
int reg_as_int = static_cast<int>(reg);
if (miscRegInfo[reg][MISCREG_BANKED]) {