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| author | William Wang <William.Wang@arm.com> | 2011-04-04 11:42:28 -0500 |
|---|---|---|
| committer | William Wang <William.Wang@arm.com> | 2011-04-04 11:42:28 -0500 |
| commit | 16fcad3907f439b8cdbaad638a8618ee7ad6a9da (patch) | |
| tree | ee8304a8947744379bdbcbd72dd4fbcc3b0fb721 /src/arch/arm/miscregs.hh | |
| parent | a679cd917ac4775979e23594de52f1bca407c08c (diff) | |
| download | gem5-16fcad3907f439b8cdbaad638a8618ee7ad6a9da.tar.xz | |
ARM: Cleanup and small fixes to some NEON ops to match the spec.
Only certain bits of the cpacr can be written, some must be equal.
Mult instructions that write the same register should do something sane
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 1e105799f..fc18fa114 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -310,6 +310,7 @@ namespace ArmISA Bitfield<23, 22> cp11; Bitfield<25, 24> cp12; Bitfield<27, 26> cp13; + Bitfield<29, 28> rsvd; Bitfield<30> d32dis; Bitfield<31> asedis; EndBitUnion(CPACR) |