diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:16 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:16 -0500 |
| commit | b8ec21455382c3b5e0e9bc8c0dbcd38b07c567e3 (patch) | |
| tree | 273490f7ecbdbf3dc6f89d3ef46c46c7f07bc24c /src/arch/arm/miscregs.hh | |
| parent | 3aea20d143ee27e0562f6f9ea3d4c1b4bbfd20f3 (diff) | |
| download | gem5-b8ec21455382c3b5e0e9bc8c0dbcd38b07c567e3.tar.xz | |
ARM: Implement ARM CPU interrupts
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 27f12c3b2..cdead8710 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -80,6 +80,7 @@ namespace ArmISA MISCREG_FPEXC, MISCREG_MVFR0, MISCREG_MVFR1, + MISCREG_SCTLR_RST, MISCREG_SEV_MAILBOX, // CP15 registers @@ -191,7 +192,7 @@ namespace ArmISA "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_mon", "spsr_und", "spsr_abt", "fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1", - "sev_mailbox", + "sctlr_rst", "sev_mailbox", "sctlr", "dccisw", "dccimvac", "dccmvac", "contextidr", "tpidrurw", "tpidruro", "tpidrprw", "cp15isb", "cp15dsb", "cp15dmb", "cpacr", |