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| author | Chander Sudanthi <Chander.Sudanthi@ARM.com> | 2011-09-13 12:06:13 -0500 |
|---|---|---|
| committer | Chander Sudanthi <Chander.Sudanthi@ARM.com> | 2011-09-13 12:06:13 -0500 |
| commit | 7c479d734922d0b9dd5c9b4404ef6d62b3d91075 (patch) | |
| tree | 769ca64c18b45fb6505d24233a601c879778ecd2 /src/arch/arm/miscregs.hh | |
| parent | 09a6e424ec966d66ec2f8cfba86d4b4141438c5a (diff) | |
| download | gem5-7c479d734922d0b9dd5c9b4404ef6d62b3d91075.tar.xz | |
CP15 c15: enable execution with accesses to c15 registers
Previously, coprocessor accesses to CP15 c15 would fault. This patch
enables accesses but prints out a warning, as the registers are not implemented.
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index f99748622..5e5735de7 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -196,6 +196,7 @@ namespace ArmISA MISCREG_ISR, MISCREG_FCEIDR, MISCREG_L2LATENCY, + MISCREG_CRN15, MISCREG_CP15_END, @@ -249,6 +250,7 @@ namespace ArmISA "dccmvau", "nsacr", "vbar", "mvbar", "isr", "fceidr", "l2latency", + "crn15", "nop", "raz" }; |