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| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-05-27 11:00:56 -0500 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-05-27 11:00:56 -0500 |
| commit | 12210ada547fa8ad10a1db4a440c25f6679809bd (patch) | |
| tree | a32d797f4463513f2910b0d94ba6940e80fc1f20 /src/arch/arm/miscregs.hh | |
| parent | 075640673963719b866e03b8ce311e221171fab6 (diff) | |
| download | gem5-12210ada547fa8ad10a1db4a440c25f6679809bd.tar.xz | |
arm: support 16kb vm granules
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index c447dcd27..938df5688 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013 ARM Limited + * Copyright (c) 2010-2014 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -1715,6 +1715,30 @@ namespace ArmISA Bitfield<20> tbi; EndBitUnion(TTBCR) + // Fields of TCR_EL{1,2,3} (mostly overlapping) + // TCR_EL1 is natively 64 bits, the others are 32 bits + BitUnion64(TCR) + Bitfield<5, 0> t0sz; + Bitfield<7> epd0; // EL1 + Bitfield<9, 8> irgn0; + Bitfield<11, 10> orgn0; + Bitfield<13, 12> sh0; + Bitfield<15, 14> tg0; + Bitfield<18, 16> ps; + Bitfield<20> tbi; // EL2/EL3 + Bitfield<21, 16> t1sz; // EL1 + Bitfield<22> a1; // EL1 + Bitfield<23> epd1; // EL1 + Bitfield<25, 24> irgn1; // EL1 + Bitfield<27, 26> orgn1; // EL1 + Bitfield<29, 28> sh1; // EL1 + Bitfield<31, 30> tg1; // EL1 + Bitfield<34, 32> ips; // EL1 + Bitfield<36> as; // EL1 + Bitfield<37> tbi0; // EL1 + Bitfield<38> tbi1; // EL1 + EndBitUnion(TCR) + BitUnion32(HTCR) Bitfield<2, 0> t0sz; Bitfield<9, 8> irgn0; |