summaryrefslogtreecommitdiff
path: root/src/arch/arm/miscregs.hh
AgeCommit message (Expand)Author
2018-05-29arch-arm: Remove unusued MISCREG_A64_UNIMPLGiacomo Travaglini
2018-05-29arch-arm: Add E2H bit to HCR_EL2 System registerGiacomo Travaglini
2018-04-19arch-arm: Add ARMv8.1 TTBR1_EL2 registerGiacomo Travaglini
2018-02-16arch-arm: IMPLEMENTATION DEFINED registerGiacomo Travaglini
2018-02-16arch-arm: Arch regs and pseudo regs distinctionGiacomo Travaglini
2018-02-07arch-arm: Change function name for banked miscregsGiacomo Travaglini
2017-04-03arm: Don't panic when checking coprocessor read/write permissionsNikos Nikoleris
2016-12-19arm: update AArch{64,32} register mappingsCurtis Dunham
2016-08-02arm: add stage2 translation supportDylan Johnson
2016-06-02arm: Rewrite ERET to behave according to the ARMv8 ARMAndreas Sandberg
2015-05-26arm: implement the CONTEXTIDR_EL2 system reg.Curtis Dunham
2014-10-29arm: Mark some miscregs (timer counter) registers at unverifiable.Ali Saidi
2014-10-01arm: Use MiscRegIndex rather than int when flatteningAndreas Hansson
2014-04-29arm: use condition code registers for ARM ISACurtis Dunham
2014-05-27arm: support 16kb vm granulesCurtis Dunham
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
2013-10-31ARM: add support for TEEHBR accessChander Sudanthi
2013-01-07arm: Remove the register mapping hack used when copying TCsAndreas Sandberg
2012-09-25arm: Use a static_assert to test that miscRegName[] is completeAndreas Sandberg
2012-07-27ARM: fix value of MISCREG_CTR returned by readMiscReg()Anthony Gutierrez
2012-06-05ARM: removed extra white spaceChander Sudanthi
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
2012-03-01ARM: Add limited CP14 support.Matt Horsnell
2011-09-13ARM: update TLB to set request packet ASID fieldDaniel Johnson
2011-09-13CP15 c15: enable execution with accesses to c15 registersChander Sudanthi
2011-09-13ARM: Implement numcpus bits in L2CTLR register.Daniel Johnson
2011-07-15ARM: Add two unimplemented miscellaneous registers.Wade Walker
2011-05-13ARM: Further break up condition code into NZ, C, V bits.Ali Saidi
2011-05-13ARM: Remove the saturating (Q) condition code from the renamed register.Ali Saidi
2011-05-13ARM: Break up condition codes into normal flags, saturation, and simd.Ali Saidi
2011-05-13ARM: Better RealView/Versatile EB platform support.Chander Sudanthi
2011-05-04ARM: Add support for MP misc regs and broadcast flushes.Ali Saidi
2011-04-04ARM: Use CPU local lock before sending load to mem system.Ali Saidi
2011-04-04ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.Ali Saidi
2011-04-04ARM: Cleanup and small fixes to some NEON ops to match the spec.William Wang
2011-04-04ARM: Cleanup implementation of ITSTATE and put important code in PCState.Ali Saidi
2011-03-25Arm: Add in a missing miscRegName.Gabe Black
2011-03-17ARM: Implement the Instruction Set Attribute Registers (ISAR).Ali Saidi
2011-02-23ARM: Adds dummy support for a L2 latency miscreg.Ali Saidi
2010-12-07O3: Make all instructions that write a misc. register not perform the write u...Giacomo Gabrielli
2010-11-15ARM: Add comment about the organization of the IT state registerAli Saidi
2010-08-25ARM: Seperate out the renamable bits in the FPSCR.Gabe Black
2010-08-25ARM: Implement CPACR register and return Undefined Instruction when FP access...Gabe Black
2010-08-23ARM: Implement some more misc registersAli Saidi
2010-06-02ARM: Added support for Access Flag and some CP15 regs (V2PCWPR, V2PCWPW, V2PC...Dam Sunwoo
2010-06-02ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR.Gabe Black
2010-06-02ARM: Some TLB bug fixes.Ali Saidi
2010-06-02ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.Ali Saidi
2010-06-02ARM: Implement ARM CPU interruptsAli Saidi
2010-06-02ARM: Make MPIDR return 0 and ignore writes.Gabe Black