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author | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-04-29 16:05:02 -0500 |
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committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-04-29 16:05:02 -0500 |
commit | 4a3f11149d791284a012af71067f6b2199aa165c (patch) | |
tree | c960b2f2c5e23fc37e238f423a8bbc3b73419213 /src/arch/arm/miscregs.hh | |
parent | 035a82ee2c7e9ee72163a6559f721b242427906d (diff) | |
download | gem5-4a3f11149d791284a012af71067f6b2199aa165c.tar.xz |
arm: use condition code registers for ARM ISA
Analogous to ee049bf (for x86). Requires a bump of the checkpoint version
and corresponding upgrader code to move the condition code register values
to the new register file.
Diffstat (limited to 'src/arch/arm/miscregs.hh')
-rw-r--r-- | src/arch/arm/miscregs.hh | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 938df5688..e14722028 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -53,25 +53,6 @@ class ThreadContext; namespace ArmISA { - enum ConditionCode { - COND_EQ = 0, - COND_NE, // 1 - COND_CS, // 2 - COND_CC, // 3 - COND_MI, // 4 - COND_PL, // 5 - COND_VS, // 6 - COND_VC, // 7 - COND_HI, // 8 - COND_LS, // 9 - COND_GE, // 10 - COND_LT, // 11 - COND_GT, // 12 - COND_LE, // 13 - COND_AL, // 14 - COND_UC // 15 - }; - enum MiscRegIndex { MISCREG_CPSR = 0, // 0 MISCREG_SPSR, // 1 |