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| author | Anthony Gutierrez <atgutier@umich.edu> | 2012-07-27 16:08:04 -0400 |
|---|---|---|
| committer | Anthony Gutierrez <atgutier@umich.edu> | 2012-07-27 16:08:04 -0400 |
| commit | 2eb6b403c976c7909a065b70ef831f4a309455b3 (patch) | |
| tree | 5192c98afcfd97382862275edc452672b01d2308 /src/arch/arm/miscregs.hh | |
| parent | ae6ab7c03ca719b7ab000ee62538fc71dd0cf8df (diff) | |
| download | gem5-2eb6b403c976c7909a065b70ef831f4a309455b3.tar.xz | |
ARM: fix value of MISCREG_CTR returned by readMiscReg()
According to the A15 TRM the value of this register is as follows (assuming 16 word = 64 byte lines)
[31:29] Format - b100 specifies v7
[28] RAZ - b0
[27:24] CWG log2(max writeback size #words) - 0x4 16 words
[23:20] ERG log2(max reservation size #words) - 0x4 16 words
[19:16] DminLine log2(smallest dcache line #words) - 0x4 16 words
[15:14] L1Ip L1 index/tagging policy - b11 specifies PIPT
[13:4] RAZ - b0000000000
[3:0] IminLine log2(smallest icache line #words) - 0x4 16 words
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 0969479ee..7af4ec605 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -529,6 +529,16 @@ namespace ArmISA Bitfield<31> l2rstDISABLE_monitor; EndBitUnion(L2CTLR) + BitUnion32(CTR) + Bitfield<3,0> iCacheLineSize; + Bitfield<13,4> raz_13_4; + Bitfield<15,14> l1IndexPolicy; + Bitfield<19,16> dCacheLineSize; + Bitfield<23,20> erg; + Bitfield<27,24> cwg; + Bitfield<28> raz_28; + Bitfield<31,29> format; + EndBitUnion(CTR) } #endif // __ARCH_ARM_MISCREGS_HH__ |