diff options
| author | Gene Wu <Gene.Wu@arm.com> | 2010-08-23 11:18:41 -0500 |
|---|---|---|
| committer | Gene Wu <Gene.Wu@arm.com> | 2010-08-23 11:18:41 -0500 |
| commit | f29e09746a1380eb43d2309de37d56beec9afab7 (patch) | |
| tree | 1a9254adf1c75aa136753a05c92e83095875772e /src/arch/arm/table_walker.cc | |
| parent | 4b9de4243943086294d7a2d7ab81a134d4fe5a49 (diff) | |
| download | gem5-f29e09746a1380eb43d2309de37d56beec9afab7.tar.xz | |
ARM: Fix Uncachable TLB requests and decoding of xn bit
Diffstat (limited to 'src/arch/arm/table_walker.cc')
| -rw-r--r-- | src/arch/arm/table_walker.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index e17e15054..6dcb387a3 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -165,8 +165,12 @@ TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _ assert(stateQueue.size() < 5); currState = NULL; } else { + Request::Flags flag = 0; + if (currState->sctlr.c == 0){ + flag = Request::UNCACHEABLE; + } port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), - NULL, (uint8_t*)&currState->l1Desc.data, (Tick)0); + NULL, (uint8_t*)&currState->l1Desc.data, (Tick)0, flag); doL1Descriptor(); f = currState->fault; } |