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| author | Daniel Johnson <daniel.johnson@arm.com> | 2011-09-13 12:06:13 -0500 |
|---|---|---|
| committer | Daniel Johnson <daniel.johnson@arm.com> | 2011-09-13 12:06:13 -0500 |
| commit | cbb23a1d3c3df9d6bed34f50a0193b93319477e6 (patch) | |
| tree | 16d36e66e10d1fcf8b08b1686cedb12cbb65769a /src/arch/arm/tlb.cc | |
| parent | 52d30813cac76b9dd69ed9c33bb4966f89c5e7a0 (diff) | |
| download | gem5-cbb23a1d3c3df9d6bed34f50a0193b93319477e6.tar.xz | |
ARM: update TLB to set request packet ASID field
Diffstat (limited to 'src/arch/arm/tlb.cc')
| -rw-r--r-- | src/arch/arm/tlb.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 942f85120..a03e445cf 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -467,6 +467,8 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, bool is_write = (mode == Write); bool is_priv = isPriv && !(flags & UserMode); + req->setAsid(contextId.asid); + DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n", isPriv, flags & UserMode); // If this is a clrex instruction, provide a PA of 0 with no fault |