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author | Dam Sunwoo <dam.sunwoo@arm.com> | 2010-06-02 12:58:18 -0500 |
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committer | Dam Sunwoo <dam.sunwoo@arm.com> | 2010-06-02 12:58:18 -0500 |
commit | 4325519fc5d1cf2bf4e57edebc739b9f79446267 (patch) | |
tree | c3fd7af2105426794760a8f0b160e1dd4b42fda1 /src/arch/arm/tlb.cc | |
parent | 2bad5138e4c1802645272a33f9b04859adac8ce2 (diff) | |
download | gem5-4325519fc5d1cf2bf4e57edebc739b9f79446267.tar.xz |
ARM: Allow multiple outstanding TLB walks to queue.
Diffstat (limited to 'src/arch/arm/tlb.cc')
-rw-r--r-- | src/arch/arm/tlb.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index acc6b416b..f0e40f690 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -387,7 +387,7 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, // Set memory attributes TlbEntry temp_te; - tableWalker->memAttrs(tc, temp_te, 0, 1); + tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1); temp_te.shareable = true; DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\ %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable, |